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d a t a sh eet preliminary speci?cation supersedes data of july 1993 file under integrated circuits, ic01 1996 jun 07 integrated circuits tea0675 dual dolby* b-type noise reduction circuit for playback applications
1996 jun 07 2 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 features dual noise reduction (nr) channels head pre-amplifiers reverse head switching automatic music search (ams) music scan equalization with electronically switched time constants dolby reference level = 387.5 mv 24 pins improved emc behaviour. general description the tea0675 is a bipolar integrated circuit that provides two channels of dolby b noise reduction for playback applications in car radios. it includes head and equalization amplifiers with electronically switchable time constants. furthermore it includes electronically switchable inputs for tape drivers with reverse heads. this device also detects pauses of music in the automatic music search (ams) scan mode, for applications with an intelligent controlled tape driver, or ams-latch mode, for applications with a simple controlled tape driver. for both modes, the delay time can be fixed externally by a resistor. the device operates with power supplies in the range of 7.6 to 12 v, output overload level increasing with increase in supply voltage. current drain varies with the following variables: supply voltage noise reduction on/off ams on/off. because of this current drain variation it is advisable to use a regulated power supply or a supply with a long time constant. quick reference data ordering information remark dolby*: available only to licensees of dolby laboratories licensing corporation, san francisco, ca94111, usa, from whom licensing and application information must be obtained. dolby is a registered trade-mark of dolby laboratories licensing corporation. symbol parameter min. typ. max. unit v cc supply voltage 7.6 - 12 v i cc supply current - 26 31 ma signal plus noise-to-noise ratio 78 84 - db type number package name description version tea0675 sdip24 plastic shrink dual in-line package; 24 leads (400 mil) sot234-1 TEA0675T so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1 sn + n --------------
1996 jun 07 3 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 block diagram handbook, full pagewidth med621 270 k w 270 k w 180 w 1 k w v cc 180 w 10 m f 100 m f 10 m f 10 m f 180 k w 180 k w 1.5 k w 330 k w 24 k w 8.2 k w 1.5 k w 24 k w 18 k w 330 k w 1 k w 8.2 k w 27 k w 120 m s 70 m s 330 nf 100 nf 330 nf 100 nf 15 nf 15 nf 4.7 nf 470 pf 10 nf 470 pf 4.7 nf 10 nf 470 pf ams (1) dolby b dolby b logic latch and rise time ams processor level detector delay time power supply eq amp. eq amp. pre amp. pre amp. 24 23 22 21 20 19 18 17 16 15 14 13 12 3 4 5 6 r t 789 1011 12 tea0675 off on off on nr eq ams output 470 pf headswitch input 21 10 m f output a 10 m f output b (1) switched to v cc for ams-scan mode. fig.1 block and application diagram.
1996 jun 07 4 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 pinning symbol pin description outa 1 output channel a inta 2 integrating ?lter channel a contra 3 control voltage channel a hpa 4 high-pass ?lter channel a sca 5 side chain channel a td 6 delay time constant eqa 7 equalizing output channel a eqfa 8 equalizing input channel a v cc 9 supply voltage ina1 10 input channel a1 (forward or reverse) v ref 11 reference voltage ina2 12 input channel a2 (reverse or forward) inb2 13 input channel b2 (reverse or forward) hs 14 head switch input inb1 15 input channel b1 (forward or reverse) gnd 16 ground eqfb 17 equalizing input channel b eqb 18 equalizing output channel b amseq 19 ams output and eq switch input scb 20 side chain channel b hpb 21 high-pass ?lter channel b contrb 22 control voltage channel b intb 23 integrating ?lter channel b outb 24 output channel b fig.2 pin configuration. handbook, halfpage outa inta contra hpa sca td eqa eqfa v cc ina1 v ref ina2 outb intb contrb hpb amseq eqb scb eqfb gnd inb1 hs inb2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 tea0675 med622
1996 jun 07 5 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 functional description noise reduction (nr) is enabled when pin hpb is open-circuit and disabled when connected to gnd via an 1.5 k w resistor. dolby b noise reduction only operates correctly if 0 db dolby level is adjusted at 387.5 mv. automatic music search (ams) scan mode is enabled when pin hpa is connected to v cc via an 1.5 k w resistor and disabled when pin hpa is open-circuit. switching ams on, internally nr is switched off simultaneously (see figs 5 and 6 for principle timing in ams-scan mode). ams-latch mode is enabled when pin hpa is connected to gnd via an 1.5 k w resistor and disabled when pin hpa is open-circuit. switching ams on, nr is switched off internally. in this mode the device detects a pause level signal, when a music level signal has appeared first (see figs 7 and 8 for principle timing). furthermore a longer rise time constant is supplied for suppressing the detection of plops on tape. the output signal at pin amseq in this mode may be applied to drive a tape driver logic circuit. equalization time constant switching (70 m s or 120 m s) is achieved when pin amseq is connected to gnd via an 18 k w resistor (120 m s), or left open-circuit (70 m s). this does not affect the ams output signal during ams mode (see fig.1). head switching is achieved when pin hs is connected (input in2 active) to gnd via a 27 k w resistor, or left open-circuit (input in1 active). the 10 m f capacitor at pin hs sets the time constants for smooth switching. in ams mode the signals of both channels are rectified and then added. this means, even if one channel signal appears inverted to the other channel, the normal ams function is ensured. pins hpb and hpa perform the function of a logic input for ams, respectively nr mode switching in both channels and provide the frequency dependent feedback of the control chain amplifier in the corresponding channel. thus it is important that no voltage is applied to pins hpb and hpa during nr on/ams off mode, otherwise this will cause irregular nr characteristics. limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. human body model (1.5 k w , 100 pf). 2. machine model (0 w , 200 pf). symbol parameter conditions min. max. unit v cc supply voltage 0 14 v v i input voltage (except pin 11) - 0.3 +v cc v t short pin 11 (v ref ) to v cc short-circuiting duration - 5s t stg storage temperature - 55 +150 c t amb operating ambient temperature - 40 +85 c v es electrostatic handling voltage for all pins note 1 - 2+2kv note 2 - 500 +500 v
1996 jun 07 6 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 characteristics v cc = 10 v; f = 20 hz to 20 khz; t amb =25 c; all levels are referenced to 387.5 mv (rms) (0 db) at test point (tp) pin outa or outb; see fig.1; nr on/ams off; eq switch in the 70 m s position; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit v cc supply voltage 7.6 10 12 v i cc supply current - 26 31 ma a m channel matching f = 1 khz; v o = 0 db; nr off - 0.5 - +0.5 db thd total harmonic distortion (2nd and 3rd harmonic) f = 1 khz; v o =0db - 0.08 0.15 % f = 10 khz; v o =10db - 0.15 0.3 % h r headroom at output v cc = 7.6 v; thd = 1%; f = 1 khz 12 -- db signal plus noise-to-noise ratio internal gain 40 db, linear; ccir/arm weighted; decode mode; see fig.25 78 84 - db psrr power supply ripple rejection v i(rms) = 0.25 v; f = 1 khz; see fig.22 52 57 - db f o frequency response; referenced to tp encode mode; see fig.25 v o = - 25 db; f = 0.2 khz - 22.9 - 24.4 - 25.9 db v o = 0 db; f = 1 khz - 1.5 0 +1.5 db v o = - 25 db; f=1khz - 17.8 - 19.3 - 20.8 db v o = - 25 db; f=5khz - 18.1 - 19.6 - 21.1 db v o = - 35 db; f = 10 khz - 24.4 - 25.9 - 27.4 db a cs channel separation v o = 10 db; f = 1 khz; see fig.23 57 63 - db a cc crosstalk between active and inactive input f = 1 khz; v o = 10 db; nr off; see fig.23 70 77 - db r l load resistance at output ac-coupled; f = 1 khz; v o = 12 db; thd = 1% 10 -- k w g v voltage gain of pre-ampli?er from pin ina1 or ina2 to pin eqfa and from pin inb1 or inb2 to pin eqfb; f = 1 khz 29 30 31 db v i(offset)(dc) dc input offset voltage - 2 - mv i i(bias) input bias current - 0.1 0.4 m a r eq equalization resistor 4.7 5.8 6.9 k w r i input resistance head inputs 60 100 - k w a v open-loop ampli?cation pin ina1 or ina2 to pin eqa and pin inb1 or inb2 to pin eqb f = 10 khz 80 86 - db f = 400 hz 104 110 - db sn + n --------------
1996 jun 07 7 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 v ref - v out dc output offset voltage at pins outa and outb nr off; pins ina1, ina2, inb1 and inb2 connected to v ref - 0.15 - +0.15 v i o dc output current pin outa to ground - 2 -- ma pin outb to v cc 0.3 -- ma z o output impedance - 80 100 w v no(rms) equivalent input noise voltage (rms value) nr off; unweighted; f = 20 hz to 20 khz; r source =0 w - 0.7 1.4 m v v td ams timing (dc level) resistor r t connected to pin td v cc - 3 - v cc v emc dc offset voltage at pins outa and outb f = 900 mhz; v i(rms) =6v; see figs 26, 27 and 28 - 40 - mv switching thresholds v nroff voltage at hpb (pin 21) nr off 0.19v cc 0.23v cc 0.25v cc v i nroff output current nr off -- 0.7 - 1ma i nron input current nr on - open 200 na v hpb(max) maximum voltage -- 0.75v cc v hpa ( pin 4) v amslon pin voltage ams-latch on 0.19v cc 0.23v cc 0.25v cc v i amslon output current -- 0.7 - 1ma v amsson pin voltage ams-scan on 0.75v cc 0.77v cc 0.81v cc v i amsson input current - 0.8 1 ma i amsoff pin current ams off - open 200 na v hpa(max) maximum voltage -- 0.75v cc v amseq ( pin 19) ams output (ams mode) v oh high level output voltage 4 4.6 5 v i oh1 high level output current note 1 +10 -- 150 m a i oh2 high level output current note 1 +0.01 -- 1ma t d minimum pulse width; delay time range see table 1 - 23 to 160 - ms v ol low level output voltage - 0.1 0.7 v i ol low level output current - 0.02 - +1 ma t r minimum pulse width rise time ams-scan mode 2 6 10 ms ams-latch mode 130 150 170 ms a m/p signal level at output for ams switching music to pause ams mode; f = 10 khz; note 2; see fig.24 - 25 - 22 - 19 db symbol parameter conditions min. typ. max. unit
1996 jun 07 8 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 notes 1. in ams off mode, pin amseq is high level, the equalization time constant will be switched by pulling approximately 200 m a out of pin amseq. this means for the device connected to pin amseq, a restriction of input current at high level less than 200 m a during ams off; otherwise the selection of the equalization time constant is disabled and fixed at 120 m s. if the connected devices consume more than 200 m a, this input has to be disconnected in ams off mode. (to ensure switching, the currents for the different switched modes are specified with a tolerance of 50 m a in chapter characteristics.) for an application with a fixed eq time constant of 120 m s the equalizing network may be applied completely external. change 8.2 k w resistor to 14 k w the internal resistor r eq = 5.8 k w is short-circuited by fixing the eq switch input at the 70 m s position (i eq70 ). 2. the high speed of the tape (ff, rew) at the tape head during ams mode causes a transformation of level and frequency of the originally recorded signal. it means a boost of signal level of approximately 10 db and more for recorded frequencies from 500 hz up to 4 khz. so the threshold level of - 22 db corresponds to signal levels in play back (pb) mode of approximately - 32 db. the ams inputs for each channel are pin sca and pin scb. as the frequency spectrum is transformed by a factor of approximately 10 to 30 due to the higher tape speed in ff, rew, the high-pass filter (4.7 nf/24 k w ) removes the effect of offset voltages but does not affect the music search function. in the application circuit (fig.1) the frequency response of the system between tape heads input, e.g. pins ina2 and inb2, to the ams input pins sca and scb is constant over the whole frequency range (see fig.3). 3. to activate the inputs in1, pin hs might be left open-circuit. in this event the dc level at pin hs is 0.775v cc . a p/m signal level at output for ams switching pause to music ams mode; f = 10 khz; - 24 - 21 - 18 db eq switch input (not ams mode) i eq70 input current time constant 70 m s active - 150 -- m a i eq120 input voltage time constant 120 m s active - 1000 -- 250 m a i eqth threshold current note 1 -- 200 -m a h ead switching v hsw pin voltage load current +90 to - 90 m a - 0.8v cc - v i hsw input current v hsw =0tov cc - 170 - +170 m a v hsw(high) high level pin voltage inputs ina1 and inb1 active; note 3 1 2 v cc + 0.5 - v cc v v hsw(low) low level pin voltage inputs ina2 and inb2 active 0 - 1 2 v cc - 0.5 v symbol parameter conditions min. typ. max. unit
1996 jun 07 9 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 table 1 blank delay time set by resistor r t at pin td general note it is recommended to switch off v cc with a gradient of 400 v/s at maximum to avoid plops on tape in the event of contact between tape and tape head while switching off. resistor value r t (k w ) delay time t d typ. (ms) tolerance (%) 68 23 20 150 42 15 180 48 15 220 56 15 270 65 10 330 76 10 470 98 10 560 112 10 680 126 10 820 142 10 1000 160 10 handbook, full pagewidth - 60 - 20 med623 10 2 10 3 10 4 10 5 - 40 - 50 - 30 (db) (hz) (1) (2) fig.3 ams threshold level. (1) ams threshold level for application circuit (fig.1). (2) ams threshold level for test circuit (fig.24).
1996 jun 07 10 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 short description music search a system for music search mainly consists of a level and a time detection (see fig.4). for adapting and decoupling the input signal will be amplified (a), then rectified (b) and smoothed with a time constant (c). so the voltage at (c) corresponds to the signal level and will be compared to the predefined pause level at the first comparator (d), the level detector. if the signal level becomes smaller than the pause level, the level detector changes its output signal. due to the output level of the level detector the capacitor of the second time constant (e) will be charged, respectively discharged. if the pause level of the input signal remains for a certain time, the voltage at the capacitor reaches a certain value, which corresponds to an equivalent time value. the voltage at the capacitor will be compared to a predefined time-equivalent voltage by the second comparator (f), the time detector. if the pause level of the input signal remains for this predefined time, the time detector changes its output level for pause found status. fig.4 integrated music search function. handbook, full pagewidth med624 comparator 1 comparator 2 t 1 t 2 input amplifier rectifier (a) (b) (c) (d) (e) (f) output v t v i level detector time detector
1996 jun 07 11 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 description of the principle timing diagram for ams-scan mode without initial input signal (see fig.5) handbook, full pagewidth med625 output signal to microprocessor 4.5 v v amseq time threshold upper threshold (hysteresis) v t v ref level threshold v l v in t r : rise time t d : delay time t b : burst time t p : pause time t f : fall time v l : voltage at level detector input pin 3 (contra) v t : voltage at time detector input pin 22 (contrb) t t t t ams on t r t d t f t b < t r t p < t d t 0 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 fig.5 ams-scan mode without initial input signal. by activating ams-scan mode, the ams output level directly indicates whether the input level corresponds to a pause level (v amseq = low) or not (v amseq = high). at t 0 the ams-scan mode is activated. without a signal at v in , the following initial procedure runs until the ams output changes to low level: due to no signal at v in the voltage at the level detector input v i (pin 3, contra) remains below the level threshold and the second time constant will be discharged (time detector input v t ). when v t passes the time threshold level, the time detector output changes to low level. now the initial procedure is completed. if a signal burst appears at t 3 , the level detector input voltage rises immediately and causes its output to charge the second time constant, which supplies the input voltage v t for the time detector. when v t passes the upper threshold level after the rise time t r (at t 4 ), the ams output changes to high. if the signal burst ends at t 5 the level detector input v i falls to its low level. when passing the level threshold at t 6 , the discharging of the second time constant begins. now the circuit measures the delay time t d , which is externally fixed by a resistor and defines the length of a pause to be detected. if no signal appears at v in within the time interval t d , the time detector output switches the ams output to low level at t 7 . if a plop noise pulse appears at v in (t 8 ) with a pulse width less than the rise time t r >t b , the plop noise will not be detected as music. the ams output remains low. similarly the system handles no music pulses t p : when music appears at t 11 with a small interruption at t 13 , this interruption will not affect the ams output for t p 1996 jun 07 12 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 description of the principle timing diagram for ams-scan mode with initial input signal (see fig.6) fig.6 ams-scan mode with initial input signal. handbook, full pagewidth med626 output signal to microprocessor 4.5 v v amseq time threshold upper threshold (hysteresis) v t v ref level threshold v l v in t r : rise time t d : delay time t b : burst time t p : pause time t f : fall time v l : voltage at level detector input pin 3 (contra) v t : voltage at time detector input pin 22 (contrb) t t t t ams on t d t f t b < t r t p < t r t 0 t 1 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 at t 0 the ams-scan mode is activated. with an input signal at v in , the following initial procedure runs until the circuit gets a steady state status. due to the signal at v in the voltage at the level detector input v i (pin 3, contra) slides to a value which is defined by a limiter. this voltage causes the level detector output charging the second time constant (time detector input v t ) to its maximum voltage level at t 1 . now the initial procedure is completed. the following behaviour does not differ from the description in section description of the principle timing diagram for ams-scan mode without initial input signal (see fig.5).
1996 jun 07 13 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 description of the principle timing diagram for ams-latch mode without initial input signal (see fig.7) fig.7 ams-latch mode without initial input signal. handbook, full pagewidth med627 output signal to power fet 4.5 v v amseq time threshold upper threshold (hysteresis) v t v ref level threshold v l v in t r : rise time t d : delay time t b : burst time t p : pause time t f : fall time v l : voltage at level detector input pin 3 (contra) v t : voltage at time detector input pin 22 (contrb) t t t t internal latch status h l t ams on t r t d t f t b < t r t p < t d t 0 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 this is similar to the description of the principle timing diagram from ams-scan mode. it only differs in its initial behaviour and its rise time t r . (please notice that the different t r does not occur in the principle timing diagrams for latch and scan mode). running in ams-latch mode, the circuit may be simply applied to drive a stop solenoid via a power fet. so the ams output signal has not to be processed by a controller. because there is no processor to make a decision whether there is a plop noise or not, for this mode the rise time t r is extended to approximately 150 ms. by activating ams-latch mode the ams output will not change to low level at t 2 if there is no initial signal at v in . a latch forces the ams output to be high until a signal appears at v in (t 4 ). after t 4 the latch will not affect the output any more until ams-latch mode is started again. the existence of the latch appears necessary if the ams output for example drives a stop solenoid via a power fet. the low output level will cause a drive of the stop solenoid. this would happen after a maximum time of t d occurred without any input signal. if there is no music on tape for a long time (e.g. at tape end), the ams mode would be activated repeatedly as long as there is no signal at v in . thus the circuit waits until first music appears before detecting the pauses.
1996 jun 07 14 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 description of the principle timing diagram for ams-latch mode with initial input signal (see fig.8) fig.8 ams-latch mode with initial input signal. handbook, full pagewidth med628 output signal to power fet 4.5 v v amseq time threshold upper threshold (hysteresis) v t v ref level threshold v l v in t r : rise time t d : delay time t b : burst time t p : pause time t f : fall time v l : voltage at level detector input pin 3 (contra) v t : voltage at time detector input pin 22 (contrb) t t t t internal latch status l h t ams on t d t f t b < t r t p < t d t 0 t 1 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 this is similar to the description in section description of the principle timing diagram for ams-scan mode with initial input signal (see fig.6). it only differs in its rise time t r and a release of its internal latch when voltage v t passes the upper threshold between t 0 and t 1 . now the initial procedure is completed. the following behaviour does not differ from the description in section description of the principle timing diagram for ams-latch mode without initial input signal (see fig.7).
1996 jun 07 15 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 internal pin configurations fig.9 pins 1 and 24: output channel. handbook, halfpage mbh506 1 + 65 w 65 w 5 v fig.10 pins 2 and 23: integrating filter. handbook, halfpage mbh507 2 v ref 0.23 v + handbook, halfpage mbh508 3 3.4 k w 1.2 k w 3.6 k w 5 v + + fig.11 pins 3 and 22: control voltage. fig.12 pins 4 and 21: high-pass filter. handbook, halfpage mbh509 4 10 k w 675 w 5 v + +
1996 jun 07 16 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 fig.13 pins 5 and 20: side chain. handbook, halfpage mbd510 5 5 v + fig.14 pin 6: delay time constant. handbook, halfpage mbh511 6 8 v 1 k w + fig.15 pins 7 and 18: equalizing output. handbook, halfpage mbh512 7 5 v 100 w 5.8 k w + fig.16 pins 8 and 17: equalizing input. handbook, halfpage mbh513 8 5 v 1 pf 10 k w +
1996 jun 07 17 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 fig.17 pin 9: supply voltage. handbook, halfpage mbh514 9 10 v fig.18 pins 10, 12, 13 and 15: input channel. handbook, halfpage mbh515 10 + 5 v 100 k w 220 w 5 v 12 pf fig.19 pin 11: reference voltage. handbook, halfpage mbh516 11 + 5 v 2.5 k w 2.5 k w fig.20 pin 14: head switch input. handbook, halfpage mbh517 14 + 8 v
1996 jun 07 18 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 fig.21 pin 19: ams output and eq switch input. handbook, halfpage mbh518 19 + 4.6 v
1996 jun 07 19 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 test and application information n dbook, full pagewidth med629 270 k w 270 k w 100 m f 1000 m f 10 m f 180 k w 180 k w 1.5 k w 24 k w 1.5 k w 24 k w 18 k w 27 k w 70 m s 330 nf 100 nf 330 nf 100 nf 15 nf 15 nf 4.7 nf 4.7 nf 100 nf (1) dolby b dolby b logic latch and rise time ams processor level detector delay time power supply eq amp. eq amp. pre amp. pre amp. 24 23 22 21 20 19 18 17 16 15 14 13 12 3 4 on off 56 r t 789 1011 12 tea0675 off on nr eq ams output 10 m f 10 k w 20 k w 20 k w 10 k w 10 m f 10 k w v cc = 10 v 0.25 v rms 1 khz 10 m f output a 10 m f output b fig.22 test circuit for power supply ripple rejection. (1) switched to v cc for ams-scan mode.
1996 jun 07 20 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 handbook, full pagewidth med630 270 k w 270 k w 100 m f 10 m f 180 k w 180 k w 24 k w 1.5 k w 24 k w 18 k w 27 k w 70 m s 330 nf 100 nf 330 nf 100 nf 15 nf 15 nf 4.7 nf 4.7 nf 100 nf dolby b dolby b logic 10 v latch and rise time ams processor level detector delay time power supply eq amp. eq amp. pre amp. pre amp. 24 23 22 21 20 19 18 17 16 15 14 13 12 3 4 5 6 r t 789 1011 12 tea0675 on off nr eq ams output 10 m f 10 k w 20 k w 20 k w 10 m f 10 m f 10 k w 200 w 10 m f output a 10 m f output b fig.23 test circuit for channel separation.
1996 jun 07 21 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 h andbook, full pagewidth med631 10 m f 270 k w 270 k w output a 100 m f 10 m f 180 k w 180 k w 1.5 k w 24 k w 1.5 k w 24 k w 18 k w 27 k w 70 m s 330 nf 100 nf 330 nf 100 nf 15 nf 15 nf 4.7 nf 4.7 nf 100 nf (1) dolby b dolby b logic latch and rise time ams processor level detector delay time power supply eq amp. eq amp. pre amp. pre amp. 24 23 22 21 20 19 18 17 16 15 14 13 12 3 4 5 6 r t 789 10 10 v 11 12 tea0675 10 m f output b eq ams output 10 m f 10 k w 20 k w 20 k w 10 m f 10 k w voltage input fig.24 test circuit for ams threshold level. (1) switched to v cc for ams-scan mode.
1996 jun 07 22 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 n dbook, full pagewidth med632 270 k w 270 k w 20 k w ams off 100 m f 10 m f 10 m f 10 m f 10 m f 10 m f 180 k w 180 k w 24 k w 10 k w 200 w 1.5 k w 24 k w 18 k w 10 k w 25 k w 25 k w 20 k w 27 k w 70 m s 330 nf 100 nf 330 nf 100 nf 15 nf 15 nf 4.7 nf 4.7 nf 100 nf 470 pf dolby b dolby b logic latch and rise time ams processor level detector delay time power supply eq amp. eq amp. pre amp. pre amp. 24 23 22 21 20 19 18 17 16 v cc v i 15 14 13 12 3 4 5 6 r t v cc v i 789 10 v 10 11 12 tea0675 encode mode off tp on nr eq ams output + - tp 10 m f output a 10 m f output b fig.25 test circuit for frequency response (channel b). decode mode: pre-amplifier 30 db and eq amplifier 10 db linear.
1996 jun 07 23 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 handbook, full pagewidth mbh497 270 k w 270 k w 100 m f 10 m f 180 k w 180 k w 24 k w 24 k w 27 k w 330 nf 100 nf 330 nf 100 nf 15 nf 15 nf 4.7 nf 4.7 nf 100 nf dolby b dolby b logic latch and rise time ams processor level detector delay time power supply eq amp. eq amp. pre amp. pre amp. 24 23 22 21 20 19 18 17 16 15 14 13 12 3 4 5 6 r t 789 1011 12 tea0675 10 m f 10 k w 20 k w 20 k w 10 m f 10 k w 200 w 10 w 40 w 200 w 470 pf 470 pf v cc = 10 v 10 m f output a 10 m f output b 200 w 200 w 470 pf 470 pf haed-switch input fig.26 emc test circuit. decode mode: pre-amplifier 30 db and eq amplifier 10 db linear.
1996 jun 07 24 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 layout of printed-circuit board for emc test circuit (for TEA0675T) fig.27 top side with components. handbook, full pagewidth mbh460 52 63 27 k w 270 k w 270 k w 10 k w 20 k w 24 k w 15 nf 100 nf 20 k w 10 k w 100 nf 15 nf 24 k w 180 k w 180 k w 40 w 10 w r t 100 nf 100 nf 4.7 nf 4.7 nf 0 w 0 w 0 w 0 w 470 pf 200 w 200 w 470 pf 470 pf 200 w 200 w 470 pf TEA0675T dimensions in mm.
1996 jun 07 25 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 fig.28 bottom side with components. oo k, full pagewidth mbh459 52 63 10 m f 10 m f 100 m f 100 m f 10 m f 10 m f 10 m f s1 mp mp mp x2 x4 x3 x1 330 nf 330 nf hfdr. dimensions in mm.
1996 jun 07 26 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 package outlines unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot234-1 92-11-17 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 22.3 21.4 9.1 8.7 3.2 2.8 0.18 1.778 10.16 10.7 10.2 12.2 10.5 1.6 4.7 0.51 3.8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 24 1 13 12 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip24: plastic shrink dual in-line package; 24 leads (400 mil) sot234-1
1996 jun 07 27 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013ad pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.050 1.4 0.055 0.42 0.39 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 92-11-17 95-01-24 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1
1996 jun 07 28 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). sdip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so r eflow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 jun 07 29 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1996 jun 07 30 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 notes
1996 jun 07 31 philips semiconductors preliminary speci?cation dual dolby* b-type noise reduction circuit for playback applications tea0675 notes
internet: http://www.semiconductors.philips.com/ps/ (1) address content source august 6, 1996 philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca49 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 83749, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 926 5361, fax. +7 095 564 8323 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220 - 5th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil, p.o. box 7383 (01064-970), tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. +886 2 382 4443, fax. +886 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. +380 44 476 0297/1642, fax. +380 44 476 6991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 708 296 8556 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 825 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 805 4455, fax. +61 2 805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 708 296 8556 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 615 800, fax. +358 615 80920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 52 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros, tel. +30 1 4894 339/911, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 648 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +1 800 234 7381, fax. +1 708 296 8556 middle east: see italy printed in the netherlands 517021/50/04/pp32 date of release: 1996 jun 07 document order number: 9397 750 00898

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